P18F87J50 19 Watchdog Timer Disabled PLL Prescaler Selection Divide by 2 (8 MHz oscillator input) Stack Overflow/Underflow Reset Enabled Extended Instruction Set Disabled Background Debug Disabled CPU System Clock Postscaler No CPU system clock divide Code Protection Disabled Oscillator Selection HS oscillator, PLL enabled, HSPLL used by USB Fail-Safe Clock Monitor Enabled Two-Speed Start-up Control bit Enabled Watchdog Timer Postscaler 1:32768 External Address Bus Shift Enabled External Memory Bus Microcontroller mode - External bus disabled Data Bus Width 16-bit external bus mode External Bus Wait Disabled ECCP2 MUX bit ECCP2/P2A is multiplexed with RC1 ECCPx MUX bit ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed wi PMP Pin Multiplex bit PMP pins placed on EMB MSSP Address Masking Mode 7-Bit Address Masking mode enable