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Chapter 4 - Assembler

The miSim DE Macro Assembler

miSim DE includes a fully featured Macro assembler that implements can support different processor mnemonics appropriate to the device being targetted. It is designed to be compatible with MPASM and similar assemblers.

The general syntax for each line of the assembly file is:

In general, each line will contain either a comment, a command for the assembler to follow, a machine instruction or will be blank. Labels are used to represent values to be used during assembly (for instance, a label might be used to represent the address of a subroutine). The assembler commands and machine instructions may take parameters, which can be labels, numbers or expressions.

Example lines for assembly:

Instruction Set

This is not meant as an introduction to the PICŪ MCU family, as there are much better written texts on the subject. However, in version 2.0 the assembler will recognise the standard Microchip mnemonics for 12- and 14-bit microcontrollers. These are detailed below. The instructions shown with a grey background are only available for 14-bit devices.

Instruction Meaning Status 14-bit Opcode 12-bit Opcode
NOP   No operation None 00 0000 0000 0000   0000 0000 0000  
CLRF f Clear f Z 00 0001 1fff ffff 0000 011f ffff
CLRW   Clear W Z 00 0001 0000 0011 0000 0100 0000
MOVLW v Move Literal to W None 11 00xx vvvv vvvv 1100 vvvv vvvv
MOVWF f Move W to f None 00 0000 1fff ffff 0000 001f ffff
MOVF f,d    Move f Z 00 1000 dfff ffff 0010 00df ffff
SWAPF f,d Swap halves f None 00 1110 dfff ffff 0011 10df ffff
COMF f,d Complement f Z 00 1001 dfff ffff 0010 01df ffff
Mathematic Instructions
ADDLW v Add literal to W C,DC,Z 11 111x vvvv vvvv - n/a -
SUBLW v Subtract W from literal C,DC,Z 11 110x vvvv vvvv - n/a -
ANDLW v AND literal and W Z 11 1001 vvvv vvvv 1110 vvvv vvvv
IORLW v Incl. OR literal and W Z 11 1000 vvvv vvvv 1101 vvvv vvvv
XORLW v Exclusive OR literal and W Z 11 1010 vvvv vvvv 1111 vvvv vvvv
ADDWF f,d Add W and f C,DC,Z 00 0111 dfff ffff 0001 11df ffff
SUBWF f,d Subtract W from f C,DC,Z 00 0010 dfff ffff 0000 10df ffff
ANDWF f,d AND W and f Z 00 0101 dfff ffff 0001 01df ffff
IORWF f,d Inclusive OR W and f Z 00 0100 dfff ffff 0001 00df ffff
XORWF f,d Exclusive OR W and f Z 00 0110 dfff ffff 0001 10df ffff
DECF f,d Decrement f Z 00 0011 dfff ffff 0000 11df ffff
DECFSZ f,d Decrement f, skip if zero None 00 1011 dfff ffff 0010 11df ffff
INCF f,d Increment f Z 00 1010 dfff ffff 0010 10df ffff
INCFSZ f,d Increment f, skip if zero None 00 1111 dfff ffff 0011 11df ffff
RLF f,d Rotate left f C 00 1101 dfff ffff 0011 01df ffff
RRF f,d Rotate right f C 00 1100 dfff ffff 0011 00df ffff
Control Instructions
CALL k Call subroutine at k None 10 0kkk kkkk kkkk 1001 kkkk kkkk
GOTO k Goto address k None 10 1kkk kkkk kkkk 101k kkkk kkkk
RETURN   Return from subroutine None 00 0000 0000 1000 - n/a -
RETFIE   Return from Interrupt None 00 0000 0000 1001 - n/a -
RETLW v Return with literal in W None 11 01xx vvvv vvvv 1000 vvvv vvvv
Bit Instructions
BCF f,b Bit clear f None 01 00bb bfff ffff 0100 bbbf ffff
BSF f,b Bit set f None 01 01bb bfff ffff 0101 bbbf ffff
BTFSC f,b Bit test, skip if clear None 01 10bb bfff ffff 0110 bbbf ffff
BTFSS f,b Bit test, skip if set None 01 11bb bfff ffff 0111 bbbf ffff
Special Instructions
SLEEP   Processor Sleep TO,PD 00 0000 0110 0011 0000 0000 0011
CLRWDT   Clear Watchdog timer TO,PD 00 0000 0110 0100 0000 0000 0100
OPTION   Load OPTION register None - n/a - 0000 0000 0010
TRIS f Tristate port f None 00 0000 0110 0fff 0000 0000 0fff

Key:

In addition to these core instructions, the standard Microchip assembler supports a number of 'Alias' instructions which are short forms of those above. Some alias instructions encode to a specific single opcode. Others may encode to two separate processor instructions. The alias instructions are listed below:

Instruction Parameters Meaning Equivalent
ADDCF f,d Add Carry to Register BTFSC 3,0
INCF f,d
ADDDCF f,d Add Digit Carry to Register BTFSC f,d
INCF 3,1
B k Branch GOTO k
BC k Branch on Carry BTFSC 3,0
GOTO k
BDC k Branch on Digit Carry BTFSC 3,1
GOTO k
BNC k Branch on No Carry BTFSS 3,0
GOTO k
BNDC k Branch on No Digit Carry BTFSS 3,1
GOTO k
BNZ k Branch on No Zero BTFSS 3,2
GOTO k
BZ k Branch on Zero BTFSC 3,2
GOTO k
CLRC   Clear Carry BCF 3,0
CLRDC   Clear Digit Carry BCF 3,1
CLRZ   Clear Zero BCF 3,2
MOVFW f Move Register to W MOVF f,0
NEGF f,d Negate Register COMF f,1
INCF f,d
SETC   Set Carry BSF 3,0
SETDC   Set Digit Carry BSF 3,1
SETZ   Set Zero BSF 3,2
SKPC   Skip on Carry BTFSS 3,0
SKPDC   Skip on Digit Carry BTFSS 3,1
SKPNC   Skip on No Carry BTFSC 3,0
SKPNDC   Skip on No Digit Carry BTFSC 3,1
SKPNZ   Skip on Non Zero BTFSC 3,2
SKPZ   Skip on Zero BTFSS 3,2
SUBCF f,d Subtract Carry from Register BTFSC 3,0
DECF f,d
SUBDCF f,d Subtract Digit Carry from Register BTFSC 3,1
DECF f,d
TSTF f Test Register MOVF f,1

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